This invention relates to the field of semiconductor devices, and more particularly, this invention relates to reducing transient enhanced diffusion in a semiconductor device.
The manufacture of BiCMOS and similar semiconductor devices that use bipolar transistors often suffer from Transient Enhanced Diffusion (TED) after the implant anneal and the related source/drain anneal. One result of Transient Enhanced Diffusion is a changed device profile and a slower device speed. It is well known that some dopant diffusion in semiconductor manufacturing can be controlled through Rapid Thermal Annealing (RTA) to enable electrical activation. However, even with Rapid Thermal Annealing processes, Transient Enhanced Diffusion still occurs during post-implant annealing.
Transient Enhanced Diffusion arises from the diffusion of dopant atoms, particular boron (B) and phosphorous (P), which also creates silicon self-interstitials that are generated by the implantation process. The implantation process damages the crystal lattice structure of a target, creating these interstitials, where the atoms occupy interstices between normal lattice sites. Rapid Thermal Annealing is known to reduce the effects of this abnormality. However, even with the Rapid Thermal Annealing, the Transient Enhanced Diffusion still increases the diffusion rate by a factor of 10 to 1,000, as caused by the excess insterstitials.
Transient Enhanced Diffusion is also a problem in MOS devices, where lateral diffusion of the drain and source implants adversely affects threshold adjust implant at a gate region. Additionally, the BiCMOS devices that use CMOS structures and associated bipolar transistors suffer from Transient Enhanced Diffusion because the bipolar structure is particularly subject to TED during the device processing and implantation stages.
It is therefore an object of the present invention to provide a semiconductor device and method of forming same that aids in suppressing Transient Enhanced Diffusion, especially with BiCMOS devices.
In accordance with the present invention, a method of forming a semiconductor device comprises the step of forming a bipolar transistor region adjacent a CMOS device region within a semiconductor substrate. Carbon is implanted in an amount of about 1013 to about 1014 cmxe2x88x922 within the bipolar transistor region of the semiconductor substrate before forming the base, emitter and collector within the bipolar transistor region. The carbon implantation of the present invention in this amount aids in suppressing Transient Enhanced Diffusion for the bipolar structure.
The bipolar transistor region is then rapid thermal annealed at a temperature ranging from about 900xc2x0 C. to about 1250xc2x0 C., and preferably about 1050xc2x0 C. This rapid thermal annealing occurs for a time period ranging from about 5 seconds to about 100 seconds, and preferably for about 10 seconds.
In still another aspect of the present invention, the method comprises the step of forming the CMOS device region as a PMOS and an NMOS and forming within the bipolar transistor region an NPN transistor, which is adjacent the NMOS. The method can also comprise the steps of forming lightly doped drain structures in the NMOS followed by forming lightly doped drain structures in the PMOS. The source and drain regions of the NMOS can be implanted first followed by implanting source and drain regions of the PMOS. A deep buried layer can be implanted within the bipolar transistor region and a pedestal and base of the bipolar transistor can then be formed by implantation.
In still another aspect of the present invention, a BiCMOS semiconductor device includes a semiconductor substrate having a CMOS and a bipolar transistor positioned adjacent the CMOS. The bipolar transistor includes a base, emitter and collector. Implanted carbon ranging in an amount from about 1013 to about 1014 cmxe2x88x922 has been implanted before the emitter and collector have been formed to aid in suppressing transient enhanced diffusion once the bipolar transistor is formed. The CMOS device region can be formed as a PMOS and an NMOS. The bipolar transistor is formed adjacent the NMOS and formed as an NPN transistor.